Cortex X925 has a 64 KB L1 data cache with 4 cycle latency like A725 companions in GB10, but takes advantage of its larger power and area budget to make that capacity go further. It uses a more sophisticated re-reference interval prediction (RRIP) replacement policy rather than the pseudo-LRU policy used on A725. Bandwidth is higher too. Arm’s technical reference manual says the L1D has “4x128-bit read paths and 4x128-bit write paths”. Sustaining more than two stores per cycle is impossible because the core only has two store-capable AGUs. Loads can use all four AGUs, and can achieve 64B/cycle from the L1 data cache. That’s competitive against many AVX2-capable x86-64 CPUs from a few generations ago. However, more recent Intel and AMD cores can use their wider vector width and faster clocks to achieve much higher L1D bandwidth, even if they also have four AGUs.
值得注意的是，LEITZPHONE 在海外的定价高达 1.6 万元人民币，国内售价尚未公布。
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Стало известно о брошенных на севере Украины наемниках ВСУ08:51
近期相继公布的财报也传递了行业的寒意：以“非洲手机之王”传音控股为例，其2025年归母净利润同比暴跌53.43%，公司直言受“存储等元器件价格上涨较多”影响。